Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 482 of 1268
REJ09B0220-0600
Bus interface
H
Internal data bus
L
Module
data bus
TCR
Bus
master
Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Bus interface
H
Internal data bus
L
Module
data bus
TMDR
Bus
master
Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Bus interface
H
Internal data bus
L
Module
data bus
TCR TMDR
Bus
master
Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]