Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 472 of 1268
REJ09B0220-0600
Bit 1
TGIEB Description
0 Interrupt requests (TGIB) by TGFB disabled (Initial value)
1 Interrupt requests (TGIB) by TGFB enabled
Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0
TGIEA Description
0 Interrupt requests (TGIA) by TGFA disabled (Initial value)
1 Interrupt requests (TGIA) by TGFA enabled
10.2.5 Timer Status Registers (TSR)
Channel 0: TSR0
Channel 3: TSR3
Bit : 7 6 5 4 3 2 1 0
— — — TCFV TGFD TGFC TGFB TGFA
Initial value : 1 1 0 0 0 0 0 0
R/W : — — — R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
Note: * Only 0 can be written, to clear the flag.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit : 7 6 5 4 3 2 1 0
TCFD — TCFU TCFV — — TGFB TGFA
Initial value : 1 1 0 0 0 0 0 0
R/W : R — R/(W)
*
R/(W)
*
— — R/(W)
*
R/(W)
*
Note: * Only 0 can be written, to clear the flag.