Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 465 of 1268
REJ09B0220-0600
Channel
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0 Description
0 0 0 0 0 Output disabled (Initial value)
1
1
0
1
TGR0C
is output
compare
register*
1
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falling edge
1 *
TGR0C
is input
capture
register
*
1
Capture input
source is
TIOCC0 pin
Input capture at both edges
1 * * Capture input
source is channel
1/count clock
Input capture at TCNT1 count-
up/count-down
*: Don’t care
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.