Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 459 of 1268
REJ09B0220-0600
Channel
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0 Description
0 0 0 0 0 Output disabled (Initial value)
1
1
0
1
TGR0D
is output
compare
register*
2
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falling edge
1 *
TGR0D
is input
capture
register
*
2
Capture input
source is
TIOCD0 pin
Input capture at both edges
1 * * Capture input
source is channel
1/count clock
Input capture at TCNT1
count-up/count-down
*
1
*: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.