Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.6.00 Sep. 27, 2007 Page 456 of 1268

REJ09B0220-0600

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or

TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer

In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and

cannot be modified.

Bit 4

BFA

Description

0 TGRA operates normally (Initial value)

1 TGRA and TGRC used together for buffer operation

Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.

Bit 3

MD3

Bit 2

MD2

Bit 1

MD1

Bit 0

MD0

Description

0 0 0 0 Normal operation (Initial value)

1 Reserved

1 0 PWM mode 1

1 PWM mode 2

1 0 0 Phase counting mode 1

1 Phase counting mode 2

1 0 Phase counting mode 3

1 Phase counting mode 4

1 * * * —

*: Don’t care

Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.

2. Phase counting mode cannot be set for channels 0 and 3. For these channels, 0 should

always be written to MD2.