Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 438 of 1268
REJ09B0220-0600
Port Function Control Register 2 (PFCR2)
Bit : 7 6 5 4 3 2 1 0
WAITPS
BREQOPS CS167E CS25E ASOD — — —
Initial value : 0 0 1 1 0 0 0 0
R/W : R/W R/W R/W R/W R/W R R R
PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to
H'30 by a reset, and in hardware standby mode.
Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. For details, see section 9.6,
Port 5.
Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. For details, see section
9.6, Port 5.
Bit 5—CS167 Enable (CS167E): Enables or disables CS
1
, CS
6
, and CS
7
output. Change the
CS167E setting only when the DDR bits are cleared to 0.
Bit 5
CS167E Description
0 CS
1
, CS
6
, and CS
7
output disabled (can be used as I/O ports)
1 CS
1
, CS
6
, and CS
7
output enabled (Initial value)
Bit 4—CS25 Enable (CS25E): Enables or disables CS
2
, CS
3
, CS
4
, and CS
5
output. Change the
CS25E setting only when the DDR bits are cleared to 0.
Bit 4
CS25E Description
0 CS
2
, CS
3
, CS
4
, and CS
5
output disabled (can be used as I/O ports)
1 CS
2
, CS
3
, CS
4
, and CS
5
output enabled (Initial value)
Bit 3—AS Output Disable (ASOD): Enables or disables AS output. For details, see section 9.13,
Port F.
Bits 2 to 0—Reserved: These bits are always read as 0.