Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 434 of 1268
REJ09B0220-0600
Pin Selection Method and Pin Functions
PF
3
/LWR
The pin function is switched as shown below according to the operating mode,
bit PF3DDR, and bit LWROD in SYSCR.
Operating
Mode
Modes 4 to 6 Mode 7
LWROD 0 1 —
PF3DDR — 0 1 0 1
Pin function
LWR
output pin
PF
3
input pin
PF
3
output pin
PF
3
input pin
PF
3
output pin
PF
2
/LCAS
*
2
/WAIT/
BREQO
The pin function is switched as shown below according to the combination of
the operating mode, and bits RMTS2 to RMTS0
*
2
, BREQOE, WAITE, ABW5
to ABW2, BREQOPS, WAITPS, and PF2DDR.
Operating Mode Modes 4 to 6 Mode 7
[DRAM space
setting]
*
2
·
[16-bit access
setting]
0 1 —
[BREQOE ·
BREQOPS]
0 1 — —
[WAITE ·
WAITPS]
0 1 0 1 — —
PF2DDR 0 1 0 1 — — — 0 1
Pin function PF
2
input
pin
PF
2
output
pin
WAIT
input
pin
*
1
Setting
pro-
hibited
BREQO
output
pin
Setting
pro-
hibited
LCAS
output
pin
*
2
PF
2
input
pin
PF
2
output
pin
Notes: 1. When DRAM space is designated for 8-bit access and PF
2
is used
as the WAIT input, this pin can be used for WAIT input when all
areas selected as DRAM space are 8-bit space and normal space
other than DRAM space is 16-bit space.
2. The DRAM interface and LCAS are not supported in the H8S/2321.
PF
1
/BACK
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF1DDR.
Operating
Mode
Modes 4 to 6 Mode 7
BRLE 0 1 —
PF1DDR 0 1 — 0 1
Pin function
PF
1
input pin
PF
1
output pin
BACK
output pin
PF
1
input pin
PF
1
output pin