Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 432 of 1268
REJ09B0220-0600
Bits 2 to 0—Reserved: These bits are always read as 0.
System Control Register (SYSCR)
Bit : 7 6 5 4 3 2 1 0
— — INTM1 INTM0 NMIEG LWROE IRQPAS RAME
Initial value : 0 0 0 0 0 0 0 1
R/W : R/W — R/W R/W R/W R/W R/W R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, controls the
LWR pin, switches the IRQ
4
to IRQ
7
input pins, and selects the detected edge for NMI. SYSCR is
initialized to H'01 by a reset, and in hardware standby mode. It is not initialized in software
standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select either of
two interrupt control modes for the interrupt controller. For details, see section 5, Interrupt
Controller.
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. For details, see
section 5, Interrupt Controller.
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. This bit is valid in
modes 4 to 6.
Bit 2
LWROD Description
0 PF
3
is designated as LWR output pin (Initial value)
1 PF
3
is designated as I/O port, and does not function as LWR output pin
Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ
4
to IRQ
7
.
For details, see section 9.6, Port 5.
Bit 0—RAM Enable (RAME): Enables or disables on-chip RAM. For details, see section 18,
RAM.