Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 406 of 1268
REJ09B0220-0600
Port B Data Register (PBDR)
Bit : 7 6 5 4 3 2 1 0
PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB
7
to PB
0
).
PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port B Register (PORTB)
Bit : 7 6 5 4 3 2 1 0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Initial value : —
*
—
*
—
*
—
*
—
*
—
*
—
*
—
*
R/W : R R R R R R R R
Note: * Determined by state of pins PB
7
to PB
0
.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB
7
to PB
0
) must always be performed on PBDR.
If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B
read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as
PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode.