Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 400 of 1268
REJ09B0220-0600
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output.
Bit 2
LWROD Description
0 PF
3
is designated as LWR output pin (Initial value)
1 PF
3
is designated as I/O port, and does not function as LWR output pin
Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ
4
to IRQ
7
.
IRQ
4
to IRQ
7
input is always performed from one of the ports.
Bit 1
IRQPAS Description
0 PA
4
to PA
7
used for IRQ
4
to IRQ
7
input (Initial value)
1 P5
0
to P5
3
used for IRQ
4
to IRQ
7
input
Bit 0—RAM Enable (RAME): Enables or disables on-chip RAM. The RAME bit is initialized
when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM disabled
1 On-chip RAM enabled (Initial value)
9.8.3 Pin Functions
Port A pins function as address outputs, interrupt input pins (IRQ
4
to IRQ
7
), and I/O ports. Port A
pin functions are shown in table 9.14.