Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 399 of 1268
REJ09B0220-0600
Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A
20
). This bit is valid
in modes 4 to 6.
Bit 0
A20E Description
0 DR is output when PA4DDR = 1
1 A
20
is output when PA4DDR = 1 (Initial value)
System Control Register (SYSCR)
Bit : 7 6 5 4 3 2 1 0
— — INTM1 INTM0 NMIEG LWROD IRQPAS RAME
Initial value : 0 0 0 0 0 0 0 1
R/W : R/W — R/W R/W R/W R/W R/W R/W
Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: This bit is always read as 0, and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select either of
two interrupt control modes for the interrupt controller. For details of the interrupt control modes,
see section 5.4.1, Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
Bit 4
INTM0
Interrupt
Control Mode Description
0 0 0 Interrupt control by I bit (Initial value)
1 — Setting prohibited
1 0 2 Interrupt control by bits I2 to I0
1 — Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG Description
0 Interrupt requested at falling edge of NMI input (Initial value)
1 Interrupt requested at rising edge of NMI input