Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 395 of 1268
REJ09B0220-0600
9.8.2 Register Configuration
Table 9.13 shows the port A register configuration.
Table 9.13 Port A Registers
Name Abbreviation R/W Initial Value Address
*
Port A data direction register PADDR W H'00 H'FEB9
Port A data register PADR R/W H'00 H'FF69
Port A register PORTA R Undefined H'FF59
Port A MOS pull-up control register PAPCR R/W H'00 H'FF70
Port A open drain control register PAODR R/W H'00 H'FF77
Port function control register 1 PFCR1 R/W H'0F H'FF45
System control register SYSCR R/W H'01 H'FF39
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
Bit : 7 6 5 4 3 2 1 0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value : 0 0 0 0 0 0 0 0
R/W : W W W W W W W W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.