Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 383 of 1268
REJ09B0220-0600
Port 5 Data Register (P5DR)
Bit : 7 6 5 4 3 2 1 0
— — — — P53DR P52DR P51DR P50DR
Initial value : Undefined Undefined Undefined Undefined 0 0 0 0
R/W : — — — — R/W R/W R/W R/W
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P5
3
to P5
0
).
Bits 7 to 4 are reserved; they return an undefined value if read, and cannot be modified.
P5DR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior
state in software standby mode.
Port 5 Register (PORT5)
Bit : 7 6 5 4 3 2 1 0
— — — — P53 P52 P51 P50
Initial value : Undefined Undefined Undefined Undefined —
*
—
*
—
*
—
*
R/W : — — — — R R R R
Note: * Determined by state of pins P5
3
to P5
0
.
PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 5 pins (P5
3
to P5
0
) must always be performed on P5DR.
Bits 7 to 4 are reserved; they return an undefined value if read, and cannot be modified.
If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read. If a port 5
read is performed while P5DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT5 contents are determined by the pin states, as
P5DDR and P5DR are initialized. PORT5 retains its prior state in software standby mode.