Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 382 of 1268
REJ09B0220-0600
9.6.2 Register Configuration
Table 9.9 shows the port 5 register configuration.
Table 9.9 Port 5 Registers
Name Abbreviation R/W Initial Value Address
*
1
Port 5 data direction register P5DDR W H'0
*
2
H'FEB4
Port 5 data register P5DR R/W H'0
*
2
H'FF64
Port 5 register PORT5 R Undefined H'FF54
Port function control register 2 PFCR2 R/W H'30 H'FFAC
System control register SYSCR R/W H'01 H'FF39
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
Port 5 Data Direction Register (P5DDR)
Bit : 7 6 5 4 3 2 1 0
— — — — P53DDR P52DDR P51DDR P50DDR
Initial value : Undefined Undefined Undefined Undefined 0 0 0 0
R/W : — — — — W W W W
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 5. Bits 7 to 4 are reserved. P5DDR cannot be read; if it is, an undefined value will be
read.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P5DDR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode. As the SCI is initialized, the pin states are determined by the
P5DDR and P5DR specifications.