Datasheet

Section 1 Overview
Rev.6.00 Sep. 27, 2007 Page 9 of 1268
REJ09B0220-0600
PE
7
/D
7
PE
6
/D
6
PE
5
/D
5
PE
4
/D
4
PE
3
/D
3
PE
2
/D
2
PE
1
/D
1
PE
0
/D
0
PD
7
/D
15
PD
6
/D
14
PD
5
/D
13
PD
4
/D
12
PD
3
/D
11
PD
2
/D
10
PD
1
/D
9
PD
0
/D
8
Port D
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Port
A
PA
7
/A
23
/IRQ
7
PA
6
/A
22
/IRQ
6
PA
5
/A
21
/IRQ
5
PA
4
/A
20
/IRQ
4
PA
3
/A
19
PA
2
/A
18
PA
1
/A
17
PA
0
/A
16
PB
7
/A
15
PB
6
/A
14
PB 5 /A
13
PB
4
/A
12
PB
3
/ A 11
PB
2
/A
10
PB
1
/A
9
PB
0
/A
8
PC
7
/A
7
PC
6
/A
6
PC
5
/A5
PC
4
/A
4
PC
3
/A
3
PC
2
/A
2
PC
1
/A
1
PC
0
/A
0
P3
5
/SCK
1
P3
4
/SCK
0
P3
3
/RxD
1
P3
2
/RxD
0
P3
1
/TxD
1
P3
0
/TxD
0
P5
3
/ADTRG/IRQ
7
/WAIT/BREQ
O
P5
2
/SCK
2
/IRQ
6
P5
1
/RxD
2
/IRQ
5
P5
0
/TxD
2
/IRQ
4
P4
7
/AN
7
/DA
1
P4
6
/AN
6
/DA
0
P4
5
/AN
5
P4
4
/AN
4
P4
3
/AN
3
P4
2
/AN
2
P4
1
/AN
1
P4
0
/AN
0
V
ref
AV
CC
AV
SS
P2
7
/PO
7
/TIOCB
5
/TMO
1
P2
6
/PO
6
/TIOCA
5
/TMO
0
P2
5
/PO
5
/TIOCB
4
/TMCI
1
P2
4
/PO
4
/TIOCA
4
/TMRI
1
P2
3
/PO
3
/TIOCD
3
/TMCI
0
P2
2
/PO
2
/TIOCC
3
/TMRI
0
P2
1
/PO
1
/TIOCB
3
P2
0
/PO
0
/TIOCA
3
P1
7
/PO
15
/TIOCB
2
/TCLKD
P1
6
/PO
14
/TIOCA
2
P1
5
/PO
13
/TIOCB
1
/TCLKC
P1
4
/PO
12
/TIOCA
1
P1
3
/PO
11
/TIOCD
0
/TCLKB
P1
2
/PO
10
/TIOCC
0
/TCLKA
P1
1
/PO
9
/TIOCB
0
P1
0
/PO
8
/TIOCA
0
P6
7
/CS
7
/IRQ
3
P6
6
/CS
6
/IRQ
2
P6
5
/IRQ
1
P6
4
/IRQ
0
P6
3
P6
2
P6
1
/CS
5
P6
0
/CS
4
PG
4
/CS
0
PG
3
/CS
1
PG
2
/CS
2
PG
1
/CS
3
PG
0
PF
7
/φ
PF
6
/AS
PF
5
/RD
PF
4
/HWR
PF
3
/LWR
PF
2
/WAIT /BREQO
PF
1
/BACK
PF
0
/BREQ
Clock pulse
generator
RAM
WDT
TPU
SCI
PPG
MD
2
MD
1
MD
0
EXTAL
XTAL
STBY
RES
WDTOVF
NMI
Bus controller
H8S/2000 CPU
DTC
Interrupt controller
Port E
Internal data bus Internal address bus
Port
B
Port
C
Port
3
Port
5
Port 4Port 2Port 1
Port
6
Port
G
Port
F
Peripheral data bus
Peripheral address bus
8-bit timer
D/A converter
A/D converter
Figure 1.2 H8S/2321 Internal Block Diagram