Datasheet

Section 9 I/O Ports
Rev.6.00 Sep. 27, 2007 Page 360 of 1268
REJ09B0220-0600
Pin Selection Method and Pin Functions
P1
2
/PO
10
/
TIOCC
0
/TCLKA
The pin function is switched as shown below according to the combination of
the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0
in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in
TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.
TPU Channel
0 Setting Table Below (1) Table Below (2)
P12DDR — 0 1 1
NDER10 — — 0 1
Pin function TIOCC
0
output P1
2
input
P1
2
output
PO
10
output
TIOCC
0
input
*
1
TCLKA input
*
2
TPU Channel
0 Setting (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR2 to
CCLR0
— — — — Other
than
B'101
B'101
Output
function
— Output
compare
output
— PWM
mode 1
output
*
3
PWM
mode 2
output
—
x: Don’t care
Notes: 1. TIOCC
0
input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =
B'10xx.
2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to
TPSC0 = B'100.
TCLKA input when channels 1 and 5 are set to phase counting
mode.
3. TIOCD
0
output is disabled.
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting
(2) applies.