Datasheet

Section 8 Data Transfer Controller

Rev.6.00 Sep. 27, 2007 Page 329 of 1268

REJ09B0220-0600

Interrupt Source

Origin of

Interrupt

Source

Vector

Number

Vector

Address

DTCE

Priority

RXI0 (receive-data-full 0) 81 H'04A2 DTCEE3 High

TXI0 (transmit-data-empty 0)

SCI

channel 0

82 H'04A4 DTCEE2

RXI1 (receive-data-full 1) 85 H'04AA DTCEE1

TXI1 (transmit-data-empty 1)

SCI

channel 1

86 H'04AC DTCEE0

RXI2 (receive-data-full 2) SCI 89 H'04B2 DTCEF7

TXI2 (transmit-data-empty 2) channel 2

90 H'04B4 DTCEF6 Low

Notes: 1. DTCE bits with no corresponding interrupt are reserved, and should be written with 0.

2. The DMAC is not supported in the H8S/2321.

start address

Next transfer

DTC vector

address

Figure 8.4 Correspondence between DTC Vector Address and Register Information