Datasheet

Section 8 Data Transfer Controller
Rev.6.00 Sep. 27, 2007 Page 328 of 1268
REJ09B0220-0600
Interrupt Source
Origin of
Interrupt
Source
Vector
Number
Vector
Address
DTCE
*
1
Priority
TGI3A (GR3A compare match/
input capture)
TPU
channel 3
48 H'0460 DTCEC5 High
TGI3B (GR3B compare match/
input capture)
49 H'0462 DTCEC4
TGI3C (GR3C compare match/
input capture)
50 H'0464 DTCEC3
TGI3D (GR3D compare match/
input capture)
51 H'0466 DTCEC2
TGI4A (GR4A compare match/
input capture)
TPU
channel 4
56 H'0470 DTCEC1
TGI4B (GR4B compare match/
input capture)
57 H'0472 DTCEC0
DMTEND0A (DMAC transfer
complete 0)
DMAC 72 H'0490 DTCEE7
DMTEND0B (DMAC transfer
complete 1
73 H'0492 DTCEE6
DMTEND1A (DMAC transfer
complete 2)
74 H'0494 DTCEE5
DMTEND1B (DMAC transfer
complete 3)
75 H'0496 DTCEE4
TGI5A (GR5A compare match/
input capture)
TPU
channel 5
60 H'0478 DTCED5
TGI5B (GR5B compare match/
input capture)
61 H'047A DTCED4
CMIA0 64 H'0480 DTCED3
CMIB0
8-bit timer
channel 0
65 H'0482 DTCED2
CMIA1 68 H'0488 DTCED1
CMIB1
8-bit timer
channel 1
69 H'048A DTCED0
DMTEND0A (DMAC transfer
complete 0)
DMAC
*
2
72 H'0490 DTCEE7
DMTEND0B (DMAC transfer
complete 1)
73 H'0492 DTCEE6
DMTEND1A (DMAC transfer
complete 2)
74 H'0494 DTCEE5
DMTEND1B (DMAC transfer
complete 3)
75 H'0496 DTCEE4
Low