Datasheet

Section 8 Data Transfer Controller
Rev.6.00 Sep. 27, 2007 Page 323 of 1268
REJ09B0220-0600
Table 8.2 Chain Transfer Conditions
1st Transfer 2nd Transfer
CHNE CHNS DISEL CR CHNE CHNS DISEL CR DTC Transfer
0 — 0 Not 0 — — — — Ends at 1st transfer
0 — 0 0 — — — — Ends at 1st transfer
0 — 1 — — — — — Interrupt request to CPU
1 0 — — 0 — 0 Not 0 Ends at 2nd transfer
0 — 0 0 Ends at 2nd transfer
0 — 1 — Interrupt request to CPU
1 1 0 Not 0 — — — — Ends at 1st transfer
1 1 — 0 0 — 0 Not 0 Ends at 2nd transfer
0 — 0 0 Ends at 2nd transfer
0 — 1 — Interrupt request to CPU
1 1 1 Not 0 — — — — Ends at 1st transfer
Interrupt request to CPU
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 8.3 outlines the functions of the DTC.