Datasheet

Section 8 Data Transfer Controller
Rev.6.00 Sep. 27, 2007 Page 318 of 1268
REJ09B0220-0600
8.2.5 DTC Transfer Count Register A (CRA)
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value :
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
R/W : — — — — — — — — — — — — — — — —
←⎯⎯⎯⎯⎯⎯⎯ CRAH ⎯⎯⎯⎯⎯⎯→ ←⎯⎯⎯⎯⎯⎯⎯ CRAL ⎯⎯⎯⎯⎯⎯→
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA register is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is
repeated.
8.2.6 DTC Transfer Count Register B (CRB)
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value :
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
R/W : — — — — — — — — — — — — — — — —
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.