Datasheet

Section 8 Data Transfer Controller
Rev.6.00 Sep. 27, 2007 Page 313 of 1268
REJ09B0220-0600
8.1.3 Register Configuration
Table 8.1 summarizes the DTC registers.
Table 8.1 DTC Registers
Name Abbreviation R/W Initial Value Address
*
1
DTC mode register A MRA —
*
2
Undefined —
*
3
DTC mode register B MRB —
*
2
Undefined —
*
3
DTC source address register SAR —
*
2
Undefined —
*
3
DTC destination address register DAR —
*
2
Undefined —
*
3
DTC transfer count register A CRA —
*
2
Undefined —
*
3
DTC transfer count register B CRB —
*
2
Undefined —
*
3
DTC enable registers DTCER R/W H'00 H'FF30 to H'FF35
DTC vector register DTVECR R/W H'00 H'FF37
Module stop control register MSTPCR R/W H'3FFF H'FF3C
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot
be located in external space. When the DTC is used, do not clear the RAME bit in
SYSCR to 0.