Datasheet

Section 8 Data Transfer Controller
Rev.6.00 Sep. 27, 2007 Page 312 of 1268
REJ09B0220-0600
8.1.2 Block Diagram
Figure 8.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM
*
. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC activation
request
Control logic
Register information
MRA MRB
CRA CRB
DAR SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
Legend:
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERF
DTVECR
DTCERA
to
DTCERF
DTVECR
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to F
: DTC vector register
Figure 8.1 Block Diagram of DTC