Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 291 of 1268
REJ09B0220-0600
7.5.11 DMAC Bus Cycles (Single Address Mode)
Single Address Mode (Read): Figure 7.27 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
DMA read
φ
A
ddress bus
DMA
dead
RD
DACK
TEND
Bus
release
DMA read DMA read DMA read
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.27 Example of Single Address Mode (Byte Read) Transfer