Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 277 of 1268
REJ09B0220-0600
ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the
DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is
sent to the CPU or DTC.
Figure 7.15 shows the operation flow in block transfer mode.
Acquire bus
ETCRAL = ETCRAL – 1
Transfer request?
ETCRAL = H'00
Release bus
BLKDIR = 0
ETCRAL = ETCRAH
ETCRB = ETCRB – 1
ETCRB = H'0000
Start
(DTE = DTME = 1)
Read address specified by MARA
MARA = MARA + SAIDE · (–1)
SAID
· 2
DTSZ
Write to address specified by MARB
MARB = MARB + DAIDE · (–1)
DAID
· 2
DTSZ
MARB = MARB – DAIDE · ( – 1)
DAID
· 2
DTSZ
· ETCRAH
MARA = MARA
– SAIDE · (–1)
SAID
· 2
DTSZ
· ETCRAH
No
Yes
No
Yes
No
Yes
No
Yes
Clear DTE bit to 0
to end transfer
Figure 7.15 Operation Flow in Block Transfer Mode