Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 273 of 1268
REJ09B0220-0600
7.5.7 Block Transfer Mode
In block transfer mode, transfer is performed with channels A and B used in combination. Block
transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in
DMACRA to 1.
In block transfer mode, a transfer of the specified block size is carried out in response to a single
transfer request, and this is executed the specified number of times. The transfer source is
specified by MARA, and the transfer destination by MARB. Either the transfer source or the
transfer destination can be selected as a block area (an area composed of a number of bytes or
words).
Table 7.11 summarizes register functions in block transfer mode.
Table 7.11 Register Functions in Block Transfer Mode
Register Function Initial Setting Operation
23 0
MARA
Source address
register
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
23 0
MARB
Destination
address register
Start address of
transfer destination
Incremented/decremented
every transfer, or fixed
0
ETCRAH
7
0
ETCRAL
7
Holds block
size
Block size
counter
Block size
Block size
Fixed
Decremented every
transfer; ETCRH value
copied when count reaches
H'00
15 0
ETCRB
Block transfer
counter
Number of block
transfers
Decremented every block
transfer; transfer ends
when count reaches
H'0000
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
ETCRB: Execute transfer count register B