Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 271 of 1268
REJ09B0220-0600
Figure 7.11 illustrates operation in normal mode.
A
ddress T
A
A
ddress B
A
Transfer
Address T
B
Legend:
Address
Address
Address
Address
Where :
Address B
B
= L
A
= L
B
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N–1))
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (N–1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
T
A
T
B
B
A
B
B
L
A
L
B
N
Figure 7.11 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests.
With auto-request, the DMAC is only activated by register setting, and the specified number of
transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be
selected. In cycle steal mode, the bus is released to another bus master each time a transfer is
performed. In burst mode, the bus is held continuously until transfer ends.