Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 242 of 1268
REJ09B0220-0600
Bit 6—Destination Address Increment/Decrement (DAID)
Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify
whether destination address register MARB is to be incremented, decremented, or left unchanged,
when data transfer is performed.
Bit 6
DAID
Bit 5
DAIDE Description
0 0 MARB is fixed (Initial value)
1 MARB is incremented after a data transfer
• When DTSZ = 0, MARB is incremented by 1 after a transfer
• When DTSZ = 1, MARB is incremented by 2 after a transfer
1 0 MARB is fixed
1 MARB is decremented after a data transfer
• When DTSZ = 0, MARB is decremented by 1 after a transfer
• When DTSZ = 1, MARB is decremented by 2 after a transfer
Bit 4—Reserved: Can be read or written to. Only 0 should be written to this bit.
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor
(activation source). The factors that can be specified differ between normal mode and block
transfer mode.
• Normal Mode
Bit 3
DTF3
Bit 2
DTF2
Bit 1
DTF1
Bit 0
DTF0 Description
0 0 0 0 — (Initial value)
1 —
1 0 Activated by DREQ pin falling edge input
1 Activated by DREQ pin low-level input
1 0 * —
1 0 Auto-request (cycle steal)
1 Auto-request (burst)
1 * * * —
*: Don't care