Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 240 of 1268
REJ09B0220-0600
7.3.4 DMA Control Register (DMACR)
DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
In full address mode, DMACRA and DMACRB have different functions.
DMACR is initialized to H'0000 by a reset, and in hardware standby mode.
DMACRA
Bit : 15 14 13 12 11 10 9 8
DTSZ SAID SAIDE BLKDIR BLKE — — —
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DMACRB
Bit : 7 6 5 4 3 2 1 0
— DAID DAIDE — DTF3 DTF2 DTF1 DTF0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 15
DTSZ Description
0 Byte-size transfer (Initial value)
1 Word-size transfer