Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 231 of 1268
REJ09B0220-0600
7.2.5 DMA Band Control Register (DMABCR)
DMABCRH
Bit : 15 14 13 12 11 10 9 8
FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DMABCRL
Bit : 7 6 5 4 3 2 1 0
DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC
channel.
DMABCR is initialized to H'0000 by a reset, and in hardware standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short
address mode or full address mode.
In short address mode, channels 1A and 1B can be used as independent channels.
Bit 15
FAE1 Description
0 Short address mode (Initial value)
1 Full address mode