Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 227 of 1268
REJ09B0220-0600
7.2.4 DMA Control Register (DMACR)
Bit : 7 6 5 4 3 2 1 0
DTSZ DTID5 RPE DTDIR DTF3 DTF2 DTF1 DTF0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in standby mode.
Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 7
DTSZ Description
0 Byte-size transfer (Initial value)
1 Word-size transfer
Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of
MAR after every data transfer in sequential mode or repeat mode.
In idle mode, MAR is neither incremented nor decremented.
Bit 6
DTID Description
0 MAR is incremented after a data transfer (Initial value)
• When DTSZ = 0, MAR is incremented by 1 after a transfer
• When DTSZ = 1, MAR is incremented by 2 after a transfer
1 MAR is decremented after a data transfer
• When DTSZ = 0, MAR is decremented by 1 after a transfer
• When DTSZ = 1, MAR is decremented by 2 after a transfer