Datasheet

Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 223 of 1268
REJ09B0220-0600
7.2 Register Descriptions (1) (Short Address Mode)
Short address mode transfer can be performed for channels A and B independently.
Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to
0, as shown in table 7.4. Short address mode or full address mode can be selected for channels 1
and 0 independently by means of bits FAE1 and FAE0.
Table 7.4 Short Address Mode and Full Address Mode (For 1 Channel: Example of
Channel 0)
FAE0 Description
0 Short address mode specified (channels A and B operate independently)
Channel 0A
MAR0A Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source, etc.
Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source, etc.
IOAR0A
ETCR0A
DMACR0A
Channel 0B
MAR0B
IOAR0B
ETCR0B
DMACR0B
1 Full address mode specified (channels A and B operate in combination)
Channel 0
MAR0A Specifies transfer source address
Specifies transfer destination address
Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.
IOAR0A
ETCR0A
DMACR0A
MAR0B
IOAR0B
ETCR0B
DMACR0B