Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 211 of 1268
REJ09B0220-0600
If a refresh request
*
and external bus release request occur simultaneously, the order of priority is
as follows:
(High) Refresh
*
> External bus release (Low)
As a refresh
*
and an external access by an internal bus master can be executed simultaneously,
there is no relative order of priority for these two operations.
Note: * The DRAM interface is not supported in the H8S/2321.
6.10.3 Pin States in External Bus Released State
Table 6.9 shows the pin states in the external bus released state.
Table 6.9 Pin States in Bus Released State
Pins Pin State
A
23
to A
0
High impedance
D
15
to D
0
High impedance
CSn
*
1
High impedance
CAS
*
3
High impedance
AS High impedance
RD High impedance
HWR High impedance
LWR High impedance
DACKm
*
2
*
3
High
Notes: 1. n = 0 to 7
2. m = 0 or 1
3. The CAS and DACKm pin functions are not supported in the H8S/2321.