Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 208 of 1268
REJ09B0220-0600
6.8.2 Pin States in Idle Cycle
Table 6.8 shows the pin states in an idle cycle.
Table 6.8 Pin States in Idle Cycle
Pins Pin State
A
23
to A
0
Contents of next bus cycle
D
15
to D
0
High impedance
CSn
*
2
High
*
1
CAS
*
4
High
AS High
RD High
HWR High
LWR High
DACKm
*
3
*
4
High
Notes: 1. Remains low in DRAM space RAS down mode or a refresh cycle.
2. n = 0 to 7
3. m = 0 and 1
4. The CAS and DACKm pin functions are not supported in the H8S/2321.