Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 203 of 1268
REJ09B0220-0600
6.8 Idle Cycle
6.8.1 Operation
When the chip accesses external space, it can insert a 1-state idle cycle (T
I
) between bus cycles in
the following two cases: (1) when read accesses in different areas occur consecutively, and (2)
when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible,
for example, to avoid data collisions between ROM, with a long output floating time, and high-
speed memory, I/O interfaces, and so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is
enabled in advanced mode.
Figure 6.31 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
T
1
A
ddress bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B Bus cycle A Bus cycle B
Long output
floating time
Data
collision
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(ICIS1 = 1 (initial value))
T
1
Address bus
φ
RD
Data bus
T
2
T
3
T
I
T
1
T
2
CS (area A)
CS (area B)
CS (area A)
CS (area B)
Figure 6.31 Example of Idle Cycle Operation (1)