Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 202 of 1268
REJ09B0220-0600
T
1
A
ddress bus
φ
CS0
AS
Data bus
T
2
T
1
T
1
Full access
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 6.30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
6.7.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait
Control.
Wait states cannot be inserted in a burst cycle.