Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 201 of 1268
REJ09B0220-0600
T
1
ddress bus
φ
CS0
AS
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 6.30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
