Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 199 of 1268
REJ09B0220-0600
6.6.2 When DDS = 0
When DRAM space is accessed in DMAC single address mode, full access (normal access) is
always performed. The DACK output goes low from the T
r
state in the case of the DRAM
interface.
In modes other than DMAC single address mode, burst access can be used when accessing DRAM
space.
Figure 6.29 shows the DACK output timing for the DRAM interface when DDS = 0.
T
p
φ
Read
Write
CSn (RAS)
HWR (WE)
D
15
to D
0
HWR (WE)
DACK
D
15
to D
0
A
23
to A
0
T
r
T
c1
T
c2
Row
CAS (UCAS)
LCAS (LCAS)
Column
Note: n = 2 to 5
Figure 6.29 DACK Output Timing when DDS = 0 (Example of DRAM Access)