Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 197 of 1268
REJ09B0220-0600
T
Rp
φ
CSn (RAS)
T
Rr
T
Rc1
T
Rw
CAS, LCAS
T
Rc2
Note: n = 2 to 5
Figure 6.26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a
SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are
output and DRAM enters self-refresh mode, as shown in figure 6.27.
When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is
cleared.
When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is
executed before self-refresh mode is entered.
T
Rp
φ
CSn (RAS)
T
Rcr
C
AS, LCAS
HWR (WE)
T
Rc3
Software
standby
Note: n = 2 to 5
High
Figure 6.27 Self-Refresh Timing