Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 191 of 1268
REJ09B0220-0600
Chip
(Address shift size set to 9 bits)
CS (RAS)
2-CAS type 4-Mbit DRAM
256-kbyte × 16-bit configuration
9-bit column address
OE
RAS
CAS UCAS
LCAS
LCAS
HWR (WE)
WE
A
9
A
8
A
8
A
7
A
7
A
6
A
6
A
5
A
5
A
4
A
4
A
3
A
3
A
2
A
2
A
1
A
1
A
0
D
15
to D
0
D
15
to D
0
Row address
input: A
8
to A
0
Column address
input: A
8
to A
0
Figure 6.19 Example of 2-CAS DRAM Connection