Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 187 of 1268
REJ09B0220-0600
6.5.7 Precharge State Control
When DRAM is accessed, an RAS precharging time must be secured. With the chip, one T
p
state
is always inserted when DRAM space is accessed. This can be changed to two T
p
states by setting
the TPC bit in MCR to 1. Set the appropriate number of T
p
cycles according to the DRAM
connected and the operating frequency of the chip. Figure 6.16 shows the timing when two T
p
states are inserted.
When the TCP bit is set to 1, two T
p
states are also used for refresh cycles.
T
p1
φ
CSn (RAS)
Read
Write
CAS, LCAS
D
15
to D
0
D
15
to D
0
A
23
to A
0
T
p2
T
r
T
c1
Row Column
T
c2
HWR (WE)
HWR (WE)
Note: n = 2 to 5
Figure 6.16 Timing with 2-State Precharge Cycle