Datasheet
Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 186 of 1268
REJ09B0220-0600
6.5.6 Basic Timing
Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4
states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or
disabling of wait insertion, and do not affect the number of access states. When the corresponding
bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle.
The 4 states of the basic timing consist of one T
p
(precharge cycle) state, one T
r
(row address
output cycle), and two T
c
(column address output cycle) states, T
c1
and T
c2
.
T
p
φ
CSn (RAS)
Read
Write
CAS, LCAS
HWR (WE)
D
15
to D
0
HWR (WE)
D
15
to D
0
A
23
to A
0
T
r
T
c1
T
c2
Row Column
Note: n = 2 to 5
Figure 6.15 Basic Access Timing