Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 185 of 1268
REJ09B0220-0600
6.5.5 Pins Used for DRAM Interface
Table 6.7 shows the pins used for DRAM interfacing and their functions.
Table 6.7 DRAM Interface Pins
Pin
With DRAM
Setting Name I/O Function
HWR WE Write enable Output When 2-CAS system is set,
write enable for DRAM space
access
LCAS LCAS Lower column address
strobe
Output Lower column address strobe
for 16-bit DRAM space access
CS2 RAS2 Row address strobe 2 Output Row address strobe when area
2 is designated as DRAM space
CS3 RAS3 Row address strobe 3 Output Row address strobe when area
3 is designated as DRAM space
CS4 RAS4 Row address strobe 4 Output Row address strobe when area
4 is designated as DRAM space
CS5 RAS5 Row address strobe 5 Output Row address strobe when area
5 is designated as DRAM space
CAS UCAS Upper column address
strobe
Output Upper column address strobe
for DRAM space access
WAIT WAIT Wait Input Wait request signal
A
12
to A
0
A
12
to A
0
Address pins Output Row address/column address
multiplexed output
D
15
to D
0
D
15
to D
0
Data pins I/O Data input/output pins