Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 184 of 1268
REJ09B0220-0600
6.5.3 Address Multiplexing
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.6
shows the relation between the settings of MXC1 and MXC0 and the shift size.
Table 6.6 Address Multiplexing Settings by Bits MXC1 and MXC0
MCR
Shift
Address Pins
MXC1 MXC0 Size A
23
to A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0 0 8 bits A
23
to A
13
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
1 9 bits A
23
to A
13
A
12
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
1 0 10 bits A
23
to A
13
A
12
A
11
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
Row
address
1
Setting
prohibited
— — — — — — — — — — — — — —
Column
address
— — — A
23
to A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
6.5.4 Data Bus
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D
15
to D
8
, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D
15
to D
0
, are enabled.
Access sizes and data alignment are the same as for the basic bus interface. For details, see section
6.4.2, Data Size and Data Alignment.