Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 177 of 1268
REJ09B0220-0600
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D
15
to D
8
Valid
D
7
to D
0
Valid
Read
HWR
LWR
D
15
to D
8
Valid
D
7
to D
0
Valid
Write
Note: n = 0 to 7
Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
