Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 175 of 1268
REJ09B0220-0600
16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D
15
to D
8
) of the data bus is used for
the even address, and the lower half (D
7
to D
0
) for the odd address.
Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D
15
to D
8
Valid
D
7
to D
0
Invalid
Read
HWR
LWR
D
15
to D
8
Valid
D
7
to D
0
High impedance
Write
High
Note: n = 0 to 7
Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)