Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 167 of 1268
REJ09B0220-0600
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
WCRH, WCRL Bus Specifications (Basic Bus Interface)
ABWCR
ABWn
ASTCR
ASTn Wn1 Wn0 Bus Width Access States
Program Wait
States
0 0 — — 16 2 0
1 0 0 3 0
1 1
1 0 2
1 3
1 0 — — 8 2 0
1 0 0 3 0
1 1
1 0 2
1 3
6.3.3 Memory Interfaces
The chip’s memory interfaces comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; a DRAM interface
*
that allows direct connection of DRAM; and a burst
ROM interface that allows direct connection of burst ROM. The interface can be selected
independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface
*
is designated functions as DRAM space, and an area for which the
burst ROM interface is designated functions as burst ROM space.
Note: * The DRAM interface is not supported in the H8S/2321.