Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 162 of 1268
REJ09B0220-0600
6.2.7 DRAM Control Register (DRAMCR)
Bit : 7 6 5 4 3 2 1 0
RFSHE RCW RMODE CMF CMIE CKS2 CKS1 CKS0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh
counter clock, and controls the refresh timer.
DRAMCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Note: In the H8S/2321 this register is reserved and must not be accessed.
Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When
refresh control is not performed, the refresh timer can be used as an interval timer.
Bit 7
RFSHE Description
0 Refresh control is not performed (Initial value)
1 Refresh control is performed
Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before-
RAS refreshing.
Bit 6
RCW Description
0
Wait state insertion in CAS-before-RAS refreshing disabled (Initial value)
RAS falls in T
Rr
cycle
1
One wait state inserted in CAS-before-RAS refreshing
RAS falls in T
Rc1
cycle
Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), selects
whether or not self-refresh control is performed in software standby mode.
Bit 5
RMODE Description
0 Self-refreshing is not performed in software standby mode (Initial value)
1 Self-refreshing is performed in software standby mode