Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 161 of 1268
REJ09B0220-0600
Bit 3
MXC1
Bit 2
MXC0 Description
0 0 8-bit shift (Initial value)
• When 8-bit access space is designated: Row address A
23
to A
8
used
for comparison
• When 16-bit access space is designated: Row address A
23
to A
9
used
for comparison
1 9-bit shift
• When 8-bit access space is designated: Row address A
23
to A
9
used
for comparison
• When 16-bit access space is designated: Row address A
23
to A
10
used
for comparison
1 0 10-bit shift
• When 8-bit access space is designated: Row address A
23
to A
10
used
for comparison
• When 16-bit access space is designated: Row address A
23
to A
11
used
for comparison
1 —
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the
number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This
setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled.
Bit 1
RLW1
Bit 0
RLW0 Description
0 0 No wait state inserted (Initial value)
1 1 wait state inserted
1 0 2 wait states inserted
1 3 wait states inserted