Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 156 of 1268
REJ09B0220-0600
Bit 3
BRSTS0 Description
0 Max. 4 words in burst access (Initial value)
1 Max. 8 words in burst access
Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for
areas 2 to 5 in advanced mode.
When DRAM space is selected, the relevant area is designated as a DRAM interface area. In the
H8S/2321 these bits are reserved and should only be written with 0.
Bit 2 Bit 1 Bit 0 Description
RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2
0 0 0 Normal space
1 Normal space DRAM space
1 0 Normal space DRAM space
1 DRAM space
1 — — —
The LCAS pin is used for the LCAS signal on the 2-CAS DRAM interface. If it is wished to use
BREQO output and WAIT input when using the LCAS signal, it is possible to switch to the P5
3
pin by means of the BREQOPS bit in PFCR2. For details, see section 9.6, Port 5 and section 9.13,
Port F.
Note: This note applies to the H8S/2323 only. If all areas selected as DRAM space are 8-bit
space, the PF
2
pin can be used as an I/O port, or as the BREQ0 or WAIT pin. However, if
PF
2
is used as the WAIT pin on the H8S/2323 only, normal space other than DRAM space
should be designated as 16-bit bus space. The RAS down mode cannot be used in this
case. Sample settings are shown below.
RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2
0 0 0 Normal space
1 Normal space
(16-bit bus)
DRAM space
(8-bit bus)
1 0 Normal space
(16-bit bus)
DRAM space
(8-bit bus)
1 DRAM space
(8-bit bus)