Datasheet

Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 148 of 1268
REJ09B0220-0600
6.1.4 Register Configuration
Table 6.2 summarizes the registers of the bus controller.
Table 6.2 Bus Controller Registers
Initial Value
Name Abbreviation R/W Reset Address
*
1
Bus width control register ABWCR R/W H'FF/H'00
*
2
H'FED0
Access state control register ASTCR R/W H'FF H'FED1
Wait control register H WCRH R/W H'FF H'FED2
Wait control register L WCRL R/W H'FF H'FED3
Bus control register H BCRH R/W H'D0 H'FED4
Bus control register L BCRL R/W H'3C H'FED5
Memory control register MCR
*
3
R/W H'00 H'FED6
DRAM control register DRAMCR
*
3
R/W H'00 H'FED7
Refresh timer counter RTCNT
*
3
R/W H'00 H'FED8
Refresh time constant register RTCOR
*
3
R/W H'FF H'FED9
Notes: 1. Lower 16 bits of the address.
2. Determined by the MCU operating mode.
3. In the H8S/2321 this register is reserved and must not be accessed.